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integrated silicon solution, inc. ? www.issi.com 1 rev. 00b 04/23/08 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls 512k x 32 high-speed asynchronous cmos static ram with 3.3v supply preliminary information april 2008 features ? high-speed access times: 8, 10, 20 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe op- tions ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single power supply v dd 1.65v to 2.2v (is61wv51232axx) speed = 20ns for v dd 1.65v to 2.2v v dd 2.4v to 3.6v (is61/64wv51232bxx) speed = 10ns for v dd 2.4v to 3.6v speed = 8ns for v dd 3.3v + 5% ? packages available: ? 90-ball minibga (8mm x 13mm ) ? industrial and automotive temperature support ? lead-free available functional block diagram description the issi is61wv51232axx/bxx and is64wv51232bxx are high-speed, 16m-bit static rams organized as 512k words by 32 bits. it is fabricated using issi 's high-perform- ance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-perfor- mance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory. the device is packaged in the jedec standard 90-ball bga (8mm x 13mm). a0-a18 ce oe we 512k x 32 memory array decoder column i/o control circuit vss vdd i/o data circuit dqa-d bw a-d ce2
2 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls pin configuration package code: b 90 ball fbga (top view) (8.00 mm x 13.00 mm body, 0.8 mm ball pitch) 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l m n p r dq1 dq2 vss vss vdd vss a0 a15 ce2 bw b vdd vss vss dq13 dq14 dq0 vdd dq3 dq6 dq7 bw a a1 a14 a17 nc dq8 dq9 dq12 vdd dq15 vss vss dq4 dq5 nc a3 a2 a13 a16 a18 vss dq10 dq11 vss vss vdd vdd dq27 dq26 nc a4 a10 a8 a9 oe vdd dq21 dq20 vdd vdd dq31 vss dq28 dq25 dq24 bw d a5 a7 a12 we dq23 dq22 dq19 vss dq16 dq30 dq29 vdd vdd vss vdd a6 a11 ce bw c vss vdd vdd dq18 dq17 pin descriptions a0-a18 address inputs dqx data i/o ce , ce2 chip enable input oe output enable input we write enable input bw x (x=a-d) byte write control v dd power vss ground nc no connection
integrated silicon solution, inc. ? www.issi.com 3 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v v dd v dd relates to gnd ?0.3 to 4.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. truth table ce ce ce ce ce ce2 oe oe oe oe oe we we we we we bwa bwa bwa bwa bwa bwb bwb bwb bwb bwb bwc bwc bwc bwc bwc bwd bwd bwd bwd bwd dq 0-7 dq 8-15 dq 16-23 dq 24-31 mode power hxxxxxxx high-z high-z high-z high-z power down (i sb ) xlxxxxxx high-z high-z high-z high-z power down (i sb ) lhlhllll data out data out data out data out read all bits (i cc ) l h l h l h h h data out high-z high-z high-z read byte a (i cc ) bits only l h l h h l h h high-z data out high-z high-z read byte b (i cc ) bits only l h l h h h l h high-z high-z data out high-z read byte c (i cc ) bits only lhlhhhhl high-z high-z high-z data out read byte d (i cc ) bits only lhxlllll data in data in data in data in write all bits (i cc ) l h x l l h h h data in high-z high-z high-z w rite byte a (i cc ) bits only l h x l h l h h high-z data in high-z high-z w rite byte b (i cc ) bits only l h x l h h l h high-z high-z data in high-z w rite byte c (i cc ) bits only l h x l h h h l high-z high-z high-z data in write byte d (i cc ) bits only lhhhxxxx high-z high-z high-z high-z selected, (i cc ) outputs disabled
4 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls dc electrical characteristics (over operating range) v dd = 2.4v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 1.8 ? v v ol output low voltage v dd = min., i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 5% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 1.65v-2.2v symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a notes: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width -2.0ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width -2.0ns). not 100% tested.
integrated silicon solution, inc. ? www.issi.com 5 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls operating range (v dd ) (is61wv51232bll) (1) range ambient temperature v dd (8 n s ) 1 v dd (10 n s ) 1 commercial 0c to +70c 3.3v + 5% 2.4v-3.6v industrial ?40c to +85c 3.3v + 5% 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. operating range (v dd ) (is64wv51232bll) range ambient temperature v dd (10 n s ) automotive ?40c to +125c 2.4v-3.6v high speed operating range (v dd ) (is61wv51232all) range ambient temperature v dd speed commercial 0c to +70c 1. 65v-2. 2v 20ns industrial ?40c to +85c 1. 65v-2. 2v 20ns automotive ?40c to +125c 1. 65v-2. 2v 20ns power supply characteristics (1) (over operating range) -8 -10 -20 symbol parameter test conditions min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. ? 110 ? 90 ? 50 ma supply current i out = 0 ma, f = f max ind. ? 115 ? 95 ? 60 auto. ? ? ? 140 ? 100 typ. (2) 60 i cc 1 operating v dd = max., com. ? 85 ? 85 ? 45 ma supply current i out = 0 ma, f = 0 ind. ? 90 ? 90 ? 55 auto. ? ? ? 110 ? 90 i sb 1 ttl standby current v dd = max., com. ? 30 ? 30 ? 30 ma (ttl inputs) v in = v ih or v il ind. ? 35 ? 35 ? 35 ce v ih , f = 0 auto. ? ? ? 70 ? 70 i sb 2 cmos standby v dd = max., com. ? 20 ? 20 ? 20 ma current (cmos inputs) ce v dd ? 0.2v, ind. ? 25 ? 25 ? 25 v in v dd ? 0.2v, or auto. ? ? ? 60 ? 60 v in 0.2v , f = 0 typ. (2) 4 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls power supply characteristics (1) (over operating range) -25 -35 symbol parameter test conditions min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. ? 30 ? 25 ma supply current i out = 0 ma, f = f max ind. ? 35 ? 30 auto. ? 60 ? 60 typ. (2) 25 i cc 1 operating v dd = max., com. ? 20 ? 20 ma supply current i out = 0 ma, f = 0 ind. ? 30 ? 30 auto. ? 50 ? 50 i sb 1 ttl standby current v dd = max., com. ? 15 ? 15 ma (ttl inputs) v in = v ih or v il ind. ? 20 ? 20 ce v ih , f = 0 auto. ? 40 ? 40 i sb 2 cmos standby v dd = max., com. ? 0.8 ? 0.8 ma current (cmos inputs) ce v dd ? 0.2v, ind. ? 1.2 ? 1.2 v in v dd ? 0.2v, or auto. ? 2 ? 2 v in 0.2v , f = 0 typ. (2) 0.1 0.1 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. operating range (v dd ) (is61wv51232bls) (1) range ambient temperature v dd (25 n s ) 1 commercial 0c to +70c 2.4v-3.6v industrial ?40c to +85c 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 25ns. when operated in the range of 3.3v + 5%, the device meets 20ns. low power operating range (v dd ) (is61wv51232als) range ambient temperature v dd speed commercial 0c to +70c 1. 65v-2. 2v 35ns industrial ?40c to +85c 1. 65v-2. 2v 35ns automotive ?40c to +125c 1. 65v-2. 2v 35ns
integrated silicon solution, inc. ? www.issi.com 7 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls ac test loads figure 1. 319 5 pf including jig and scope 353 output 3.3v figure 2. z o = 50 1.5v 50 output 30 pf including jig and scope ac test conditions (high speed) parameter unit unit unit (2.4v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v dd -0.3v 0.4v to v dd -0.3v 0.4v to v dd -0.2v input rise and fall times 1.5ns 1.5ns 1.5ns input and output timing v dd /2 v dd /2 + 0.05 v dd /2 and reference level (v ref ) output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2
8 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls read cycle switching characteristics (1) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t rc read cycle time 8 ? 10 ? ns t aa address access time ? 8 ? 10 ns t oha output hold time 2.5 ? 2.5 ? ns t ace ce access time ? 8 ? 10 ns t doe oe access time ? 5.5 ? 6.5 ns t hzoe (2) oe to high-z output ? 3 ? 4 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzce (2 ce to high-z output 0 3 0 4 ns t lzce (2) ce to low-z output 3 ? 3 ? ns t ba byte enable to data valid ? 5.5 ? 6.5 ns t lzb byte enable to low-z 0 ? 0 ? ns t hzb byte enable to high-z 0 3 0 3 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage.
integrated silicon solution, inc. ? www.issi.com 9 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls read cycle switching characteristics (1) (over operating range) -20 ns symbol parameter min. max. unit t rc read cycle time 20 ? ns t aa address access time ? 20 ns t oha output hold time 2.5 ? ns t ace ce access time ? 20 ns t doe oe access time ? 8 ns t hzoe (2) oe to high-z output 0 8 ns t lzoe (2) oe to low-z output 0 ? ns t hzce (2 ce to high-z output 0 8 ns t lzce (2) ce to low-z output 3 ? ns t ba byte enable to data valid ? 8 ns t lzb byte enable to low-z 0 ? ns t hzb byte enable to high-z 0 3 ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4 v to v dd -0.3v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
10 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.e p s address oe bw a-d ce d out t hzce t hzb t ba t lzb read cycle no. 2 (1,3) ( ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. ? www.issi.com 11 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls write cycle switching characteristics (1,3) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t wc write cycle time 8 ? 10 ? ns t sce ce to write end 6.5 ? 8 ? ns t aw address setup time 6.5 ? 8 ? ns to write end t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwb bw a-d valid to end of write 6.5 ? 8 ? ns t pwe 1 we pulse width 6.5 ? 8 ? ns t pwe 2 we pulse width ( oe = low) 8.0 ? 10 ? ns t sd data setup to write end 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 3.5 ? 5 ns t lzwe (2) we high to low-z output 2 ? 2 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the sign al that terminates the write. shaded area product in development
12 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls write cycle switching characteristics (1,2) (over operating range) -20 ns symbol parameter min. max. unit t wc write cycle time 20 ? ns t sce ce to write end 12 ? ns t aw address setup time 12 ? ns to write end t ha address hold from write end 0 ? ns t sa address setup time 0 ? ns t pwb bw a-d valid to end of write 12 ? ns t pwe 1 we pulse width ( oe = high) 12 ? ns t pwe 2 we pulse width ( oe = low) 17 ? ns t sd data setup to write end 9 ? ns t hd data hold from write end 0 ? ns t hzwe (3) we low to high-z output ? 9 ns t lzwe (3) we high to low-z output 3 ? ns notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 0.3v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. ? www.issi.com 13 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls ac waveforms write cycle no. 1 (1,2) ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
14 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls ac waveforms write cycle no. 2 ( we controlled. oe is high during write cycle) (1,2) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce bw a-d we d out d in oe data in valid t lzwe t sd ub_cewr2.e p s write cycle no. 3 ( we controlled. oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce bw a-d we d out d in oe data in valid t lzwe t sd ub_cewr3.eps
integrated silicon solution, inc. ? www.issi.com 15 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls ac waveforms write cycle no. 4 (byte controlled, back-to-back write) (1,3) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce bw a-d we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha notes: 1. the internal write time is defined by the overlap of and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the t sa , t ha , t sd , and t hd timing is referenced to the rising or falling edge of the signal that terminates the write. 2. tested with oe high for a minimum of 4 ns before we = low to place the i/o in a high-z state. 3. we may be held low across many address cycles and the bw a-d pins can be used to control the write function.
16 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls data retention waveform ( ce controlled) v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd 1.65v 1.4v data retention mode data retention switching characteristics (high speed) (is61wv51232all/bll) symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, ce v dd ? 0.2v ind. ? 25 ma auto. ? 60 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns
integrated silicon solution, inc. ? www.issi.com 17 rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls data retention waveform ( ce controlled) v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd 1.65v 1.4v data retention mode data retention switching characteristics (low power) (is61wv51232als/bls) symbol p arameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, ce v dd ? 0.2v ind. ? 1.2 ma auto. ? 2 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns
18 integrated silicon solution, inc. ? www.issi.com rev. 00b 04/23/08 is61wv51232all/als is61wv51232bll/bls is64wv51232bll/bls ordering information industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 (8 1 ) IS61WV51232BLL-10BI 90-ball bga (8mm x 13mm) is61wv51232bll-10bli 90-ball bga (8mm x 13mm), lead-free note: 1. speed = 8ns for v dd = 3.3v + 5%. speed = 10ns for v dd = 2.4v - 3.6v industrial range: -40c to +85c voltage range: 1.65v to 2.2v speed (ns) order part no. package 20 is61wv51232all-20bi 90-ball bga (8mm x 13mm) automotive range: -40c to +125c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 is64wv51232bll-10ba3 90-ball bga (8mm x 13mm)
0.45 0.80 d1 2. reference document : jedec mo-207 1. controlling dimension : mm . note : package outline 08/14/2008

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